Memory Leakage Control Circuit and Method

ABSTRACT

In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and comprises a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.

BACKGROUND

1. Technical Field

The present disclosure relates generally to semiconductor memories. Moreparticularly, and not by way of any limitation, the present disclosureis directed to a source-biasing scheme for reducing leakage in StaticRandom Access Memory (SRAM) cells.

2. Description of Related Art

Static Random Access Memory (SRAM) devices containing a plurality ofmemory cells are typically configured as an array having rows andcolumns, with one or more I/Os (i.e., ×4, ×8, ×16, etc. configurations).Also, such memories may be provided in a multi-bank architecture forapplications where high density, high speed, and low power are required.Regardless of the architecture and type, each SRAM cell is operable tostore a single bit of information. To access this information, a memorysystem activates all memory cells in a given row by driving a wordlineassociated therewith and outputs the data onto bitlines associated witha selected column for providing the stored data value to the selectedoutput. Once the data is disposed on the bitlines, voltage levels on thebitlines begin to separate to opposite power supply rails (e.g., V_(DD)and ground), and a sense amp is utilized to latch the logic levelssensed on the bitlines after they are separated by a predeterminedvoltage difference, typically 10% or less of V_(DD). Furthermore, thesense amp may be provided as a differential sense amp, with each of thememory cells driving both a data signal and a data-bar signal on thecomplementary bitlines (i.e., data lines) associated with each column.

In operation, prior to activating the memory cells, the bitlines areprecharged and equalized to a common value. Once a particular row andcolumn are selected, the memory cell corresponding thereto is activatedsuch that it pulls one of the data lines toward ground, with the otherdata line remaining at the precharged level, typically V_(DD). The senseamp coupled to the two complementary bitlines senses the differencebetween the two bitlines once it exceeds a predetermined value and thesensed difference is indicated to the sense amp as the differing logicstates of “0” and “1”.

As the transistor device sizes continue to decrease, e.g., 0.13μ orsmaller, several issues begin to emerge with respect to the operation ofSRAM cells, chiefly because at such dimensions the devices suffer fromhigh values of leakage in the off state in standby mode. Essentially,these devices are no longer ideal switches; rather they are closer tosieves, having a non-negligible constant current flow path from drain tosource or from drain/source to substrate even in the off state. The highleakage causes two major problems. First, because of the generation oflarge static current as leakage, there is increased static powerconsumption as a result. Second, which is more serious, is the issue ofincorrect data reads from the SRAM cells. The accumulated leakagecurrent from all the bitcells in a selected column is now comparable tothe read current, thereby significantly eroding the bitline differentialrequired for reliable sensing operations.

SUMMARY

In one aspect, the present disclosure is directed to a static randomaccess memory (SRAM) operable with a first voltage and a second voltage.The SRAM comprises a plurality of SRAM cells arranged in rows andcolumns, with each SRAM cell coupled to a respective wordline,respective complementary bitlines, and a source line. The SRAM alsocomprises a control circuit connected between the source line and thesecond voltage, so that the control circuit is selectively operable in aworking mode in which data in said plurality of SRAM cells can beaccessed and is also operable in a shutdown mode in which the sourceline is allowed to float to a voltage level that is substantially equalto the first voltage.

In another aspect, the present disclosure is directed to a controlcircuit for an SRAM that is operable between a first voltage and asecond voltage. The control circuit comprises a first means forselectively connecting a source line of the SRAM to the second voltage,a second means for selectively connecting the source line to a thirdvoltage that is between the first and second voltages, and a third meansfor selectively allowing the source line to float to a level that issubstantially equal to the first voltage.

In a further aspect, the present disclosure is directed to a memoryleakage control method operable with an SRAM that operates between afirst voltage and a second voltage, with the SRAM including a pluralityof SRAM cells arranged in rows and columns, each SRAM cell being coupledto a respective wordline, respective complementary bitlines, and asource line. The method comprises the operations of selectivelyconnecting the source line to the second voltage, selectively connectingthe source line to a third voltage that is between the first and secondvoltages, and selectively allowing the source line to float to a valuethat is substantially equal to the first voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure may be had byreference to the following Detailed Description when taken inconjunction with the accompanying drawings wherein:

FIG. 1 depicts an exemplary embodiment of a source-biased SRAM cell inaccordance with the teachings of the present patent application;

FIG. 2 depicts an exemplary memory array portion comprisingsource-biased SRAM cells according one embodiment of the present patentapplication;

FIG. 3 depicts a memory leakage control circuit for a memory core;

FIG. 4 depicts a memory leakage control circuit for a memory core inaccordance with the teachings of the present patent application;

FIG. 5 depicts an exemplary memory array and control circuit inaccordance with one embodiment of the present patent application;

FIG. 6 depicts an exemplary memory array and control circuit inaccordance with one embodiment of the present patent application; and

FIG. 7 depicts a memory leakage control method in accordance with oneembodiment of the present patent application.

DETAILED DESCRIPTION OF THE DRAWINGS

In the drawings, like or similar elements are designated with identicalreference numerals throughout the several views thereof, and the variouselements depicted are not necessarily drawn to scale. Referring now toFIG. 1, depicted therein is an exemplary embodiment of a source-biasedSRAM cell 100 in accordance with the teachings of the present disclosurewherein leakage may be advantageously reduced without disturbing theintegrity of stored data and wherein leakage may be further reduced whenthe retention of stored data is not a concern. As illustrated, SRAM cell100 is provided with a pair of complementary bitlines, BL 114A and /BL114B where each of the complementary bitlines may be coupled toappropriate precharge circuitry (not shown in this Figure) such that itis pulled to a power supply rail or a reference voltage source(typically V_(DD) or any portion thereof) when the precharge circuitryis activated.

The memory cell 100, also referred to as a bitcell, comprises a 4T-CMOSlatch 102 that includes a pair of cross-coupled inverters to form a pairof data nodes 108A and 108B. A first P-channel field effect transistor(P-FET) 106A operating as a pull-up device of one of the inverters hasits source/drain terminals connected between V_(DD) and first data node108A, with the gate thereof connected to second data node 108B. As iswell known, the data nodes 108A and 108B operate as the twocomplementary storage nodes in the memory cell 100. An N-channel FET(N-FET) 104A operating as a pull-down device has its drain connected todata node 108A and its source connected to a source bias control line(SL) 116 that is switchably connected to a bias potential as will bedescribed in greater detail hereinbelow. The gate of N-FET 104A iscoupled to second data node 108B. With respect to the other inverter, asecond P-FET 106B is operable as a pull-up device having itssource/drain terminals connected between V_(DD) and data node 108B, withthe gate thereof connected to data node 108A. A second N-FET 104B isoperable as a pull-down device wherein the drain is coupled to data node108B and the source is commonly connected to source bias control line116.

A first N-FET access device 112A is disposed between BL 114A and datanode 108A, with the gate thereof coupled to wordline (WL) 110. Insimilar fashion, a second N-FET access device 112B has the source/drainthereof connected between /BL 114B and data node 108B, wherein its gateis also driven by WL 110. The cross-coupled inverters of the memory cellform latch 102, where nodes 108A and 108B are operable to hold logiclevels that correspond to stored data.

In one embodiment of a memory standby mode, WL 110 is held low and theprecharge circuitry associated with the bitlines is activated so as topull the bitlines to a predetermined high voltage. Further, SL 116 israised to a select potential (having a range approximately from around100 millivolts to 300 millivolts, the value being determined such thatthe logic levels that correspond to stored data at nodes 108A and 108Bare not disturbed, which depends on the SRAM cell technology, operatingvoltage levels, device sizing, et cetera). Because of the biasing of thesources of the N-FET pull-down devices 104A and 104B by SL 116, both thegate leakage and sub-threshold leakage through bitcell 100 issignificantly reduced.

In one embodiment of a memory shutdown mode, WL 100 is held low and theprecharge circuitry associated with the bitlines is activated so as topull the bitlines to the predetermined high voltage. In shutdown mode,source line SL 116 is isolated from the source voltage and is allowed tofloat. Due to leakage in bitcell 100 and the other bitcells connected tothe source line, the voltage on source line 116 will float up until itstabilizes at a point at or near V_(DD). When SL 116 stabilizes, therewill be essentially no gradient across bitcell 100, so further leakagewill be minimized. In this state, it will be understood that the abilityto store differential values in latch 102 can be impaired and any storeddata will be lost.

FIG. 2 depicts an exemplary SRAM array portion 200 comprisingsource-biased memory cells (SBMCs) according to one embodiment of thepresent disclosure. As illustrated, 16 bitcells, SBMC(0,0) to SBMC(3,3),are disposed in a 4-by-4 array, where bitcells of each row areassociated with a respective WL corresponding to the row. In FIG. 2, SL0to SL3 exemplify four commonly coupled source bias control lines, eachoperating with respect to a particular column of bitcells. Coupled tosource line 202 is control circuit 204, which may selectively connect SL202 and SRAM array portion 200 to the lower power rail or to a voltagethat is above the lower power rail. Control circuit 204 may alsoselectively isolate SL 202 from either of these voltage sources.

FIG. 3 depicts a leakage control circuit 300 for a memory array 310.Memory array 310 is a static random access memory and can be organizedin rows and columns, such as is shown in the exemplary memory of FIG. 2.As illustrated, leakage control circuit 300 is divided into twosections, 300A and 300B. Section 300A of the leakage control circuitcontains P-FET P1 and is connected between memory array 310 and theupper supply rail that is generally designated V_(DD). In order toprovide V_(DD) to memory array 310, P1 is typically implemented as alarge transistor. Additionally, although P1 is shown as a single P-FET,an implementation of this circuit may be realized as an array of P-FETs,connected as necessary to supply V_(DD) to the entire memory array. Forexample, a row of P-FETS may be connected in parallel, each providingV_(DD) to a portion of memory 310. A second section 300B of the leakagecontrol circuit contains two N-FETs, N1 and N2. Transistor N1 isconnected to the source line SL of the memory array and to the lowerpower rail, such as ground. Transistor N2 is also connected to thesource line of the memory array and to the lower power rail, but in N2,the gate and drain of the transistor are connected to each other so thatN2 acts as a diode.

In operation, when signal 312 is high so that P1 is turned off, no poweris available to memory array 310 and the memory is in shutdown mode,with no ability to retain data. When signal 312 is low so thattransistor P1 is on, memory array 310 receives power and has thecapability of retaining any data that is stored therein. Additionally,depending on the connection to the lower power rail, memory array 310may also have the capability of reading and writing data. When signal312 is held low and signal 314 goes high, transistors N1 and P1 are bothon and memory array 310 is connected to both V_(DD) and ground. Thisprovides the full voltage drop across the memory array, allowing data tobe read from and written to the cells of the array in a working mode.Although data is optimally retained in this mode, leakage across memoryarray 310 is at its highest level. Finally, when both signals 312, 314are low, so that P1 is on but N1 is off, the voltage on the source line,and thus on the drain of transistor N2, will rise toward V_(DD).Transistor N2 acts as a diode, so that once the voltage on SL reaches avalue equal to the threshold value VT of transistor N2, this transistorwill turn on, holding the voltage on the source line at a value ofapproximately VT. This provides a sleep mode in which the differencebetween V_(DD) and the voltage on the source line is reduced,effectuating a drop in leakage across the storage transistors of eachbitcell.

Although only one each of transistors N1 and N2 are shown in the Figure,each of these transistors may be replicated as multiple N-FET devices ina row. For example, the source line of a plurality of columns of array310 may be connected together as a set as shown in FIG. 2, with each setbeing connected to a separate control circuit 300B. One skilled in theart would understand that circuit 300B may be implemented in a number ofways according to the requirements of the specific memory (e.g., I/Oconfiguration, column banking, row banking, etc.).

FIG. 4 depicts a memory array 410 that operates between a first voltage,generally denoted V_(DD), and a second voltage, generally denoted GND,in accordance with another embodiment of the present patent application.It will be understood that although the second voltage may be aconnection to ground, memory array 410 can be operated with first andsecond voltages that do not include ground, but which provide thenecessary voltage difference to store information in the bitcells.Memory array 410 is connected to memory leakage control circuit 400. Inone embodiment, memory array 410 can be an SRAM, with SRAM bitcellsarranged in rows and columns and with each bitcell connected to acorresponding wordline and to a pair of complementary bitlines. A commonsource line may connect a number of bitcells together, along the rows orthe columns, e.g., as shown in FIG. 2. In the embodiment illustrated,memory array 410 is connected to V_(DD), preferably without anintervening P-FET. The leakage control circuit 400 is connected betweenmemory array 410 and the lower power rail, shown here as the groundconnection GND. In one embodiment, leakage control circuit 400advantageously contains three transistors, all of these being N-FETdevices. The N-FETs forming leakage control circuit 400 may require lessarea on the chip than a design using both N-FETs and P-FETs, such as,for example, the embodiment shown in FIG. 3. Transistor N1 is connectedbetween the memory array 410 and the ground connection GND and iscontrolled by signal 414. Transistors N2 and N3 are connected generallyin series between memory array 410 and the ground connection GND. Thegate of transistor N3 is controlled by signal 416, while the gate anddrain of transistor N2 are connected together.

In operation, memory array 410 is in a working mode when signal 414 ishigh, turning on transistor N1, with suitable first and second voltagesbeing applied. This connects source line SL to ground and provides thenecessary voltage gradient across the memory array. In the working mode,data can be read from and written to memory array 410 and will beoptimally retained, but leakage is high due to the differential acrossthe transistors. Thus, transistor N1 forms a means for selectivelyconnecting the source line to the second voltage.

A sleep mode is operative when signal 414 is low and signal 416 is high,turning off transistor N1 and turning on transistor N3. As the circuitmoves from working mode to sleep mode, the voltage on SL can rise, dueto leakage across the array, until the voltage is approximately thethreshold voltage VT of transistor N2, at which point N2 will turn on.Alternatively, further circuitry may be added to drive SL to the valueof VT more quickly. As in circuit 300B, N2 acts as a diode and will holdthe voltage on the source line SL at approximately VT, i.e., a diodedrop above ground. Thus, transistors N2 and N3 provide a means forselectively connecting the source line to a third voltage that isbetween the first and second voltages. In one embodiment, the firstvoltage is equal to 1.2 volts, the second voltage is 0 volts, and thethird voltage is 0.6 volts. In sleep mode, data is retained in thebitcells and the leakage is significantly reduced, although no data canbe read or written.

A shutdown mode is operative when both signals 414, 416 are low, turningoff transistors N1 and N2. Memory array 410 is isolated from the secondvoltage. In a shutdown mode, source line SL can float, due to cellleakage, to a level at or near V_(DD). As the voltage on SL approachesV_(DD), little or no gradient exists to drive further leakage currentand the leakage drops to near zero. At the same time the bitcells willlose their ability to store information and all data will be lost. Thus,transistors N1 and N3 provide a means for selectively allowing thesource line to float to the level of the first voltage.

Although control circuit 400 is shown as a single circuit of threetransistors attached to source line SL, there is generally a need formore than a single control circuit to provide connection to the lowerpower rail. In practice, memory array 410 may be sub-divided into groupsof cells, with each group of cells having a common source line connectedto a respective control circuit. FIG. 2 discloses one such possibilityin which the source lines of four columns of the memory are connectedtogether and served by control circuit 204. FIGS. 5 and 6 disclose otherpossible arrangements.

With reference to FIG. 5, a memory array 510 and control circuit 500 aredepicted according to one embodiment of the disclosure, with eachbitcell depicted by a square having connections to a wordline,complementary bitlines, and a source line. Memory array 510 isconfigured with a specific I/O basis, i.e., the number of bits read orwritten with each memory operation, generally 4, 8, 16, 32, 64, etc. Thememory array is logically divided into groups of columns 512-0 through512-(N−1), with each group 512-x containing a number of columnsaccording to the I/O basis. In this embodiment, a respective controlcircuit 500-x is connected to the source line of each group 512-x,thereby forming global control circuitry 500 for the entire array 510.

With reference to FIG. 6, a memory array 610 and control circuit 600 aredepicted according to one embodiment of the disclosure. In thisembodiment, memory array 610 is organized as multiple banks 612-0through 612-(N−1), with each bank containing multiple rows of SRAMcells, e.g., 128, 256, 512 or 1024 rows, etc. Within each bank 612-x,the source lines for all bitcells are connected together and this commonsource line is connected to a respective control circuit 600-x. Oneskilled in the art will understand that the arrangement of memory andcontrol circuits in each of these exemplary embodiments are forillustration only.

Turning to FIG. 7, a memory leakage control method operable with an SRAMthat operates between a first voltage and a second voltage is depictedin accordance with one embodiment of the present patent application,wherein each SRAM cell is coupled to a respective wordline, respectivecomplementary bitlines, and a source line. In block 710, the source lineis selectively connected to the second voltage, e.g., to ground. Thisprovides the working mode discussed above. Similarly, in block 715, thesource line is selectively connected to a third voltage that is betweenthe first and second voltages. The third voltage may be, for example, adiode voltage drop above the second voltage. Connection to this thirdvoltage provides the sleep mode. Likewise, in block 720, the source lineis selectively isolated from the second voltage, allowing the sourceline to float to a value or level that is equal or substantially equalto the first voltage, providing the shutdown mode. Although these blocksare shown sequentially, there is no specific order in which they areperformed. Rather, the method may respond to the specific conditionspresent in a memory circuit to provide the desired functional mode orstate therein. Further, although an embodiment of the control circuithaving all N-FETs has been described in detail hereinabove, it should beappreciated that in certain arrangements, an all P-FET design may beimplemented with suitable signal logic for providing appropriatefunctional modes.

It is believed that the operation and construction of the embodiments ofthe present disclosure will be apparent from the foregoing DetailedDescription. It should be readily understood that various changes andmodifications could be made therein without departing from the scope ofthe present disclosure as set forth in the following claims.

1. A static random access memory (SRAM) operable with a first voltageand a second voltage, said SRAM comprising: a plurality of SRAM cellsarranged in rows and columns, each SRAM cell being coupled to arespective wordline, respective complementary bitlines, and a sourceline; and a control circuit connected between said source line and saidsecond voltage, wherein said control circuit is selectively operable ina working mode in which data in said plurality of SRAM cells can beaccessed, and a shutdown mode in which said source line is allowed tofloat to a level that is substantially equal to said first voltage. 2.The static random access memory according to claim 1, wherein saidcontrol circuit comprises three N-channel transistors.
 3. The staticrandom access memory according to claim 1, wherein said control circuitcomprises a first transistor that is connected to said second voltageand to said source line and a second transistor that is connected tosaid second voltage and is connected to said source line through a thirdtransistor.
 4. The static random access memory according to claim 3,wherein a gate and a drain of said second transistor are connectedtogether.
 5. The static random access memory according to claim 1,wherein said control circuit is further operable in a sleep mode thatretains data and decreases leakage within said SRAM.
 6. The staticrandom access memory according to claim 5, wherein in said sleep mode,said source line stabilizes at about a diode drop above said secondvoltage.
 7. The static random access memory according to claim 1,wherein said SRAM is divided into a plurality of banks of cells, eachbank being connected to a respective source line and a respectivecontrol circuit.
 8. The static random access memory according to claim1, wherein said source line and said control circuit are connected to ncolumns of said memory on a per input/output (I/O) basis.
 9. The staticrandom access memory according to claim 8, wherein said n is selectedfrom 4, 8, 16, 32, and 64 columns.
 10. The static random access memoryaccording to claim 1, wherein said second voltage comprises 0 volts. 11.A control circuit for a static random access memory (SRAM) that isoperable between a first voltage and a second voltage, said controlcircuit comprising: first means for selectively connecting a source lineof said SRAM to said second voltage; second means for selectivelyconnecting said source line to a third voltage that is between saidfirst voltage and said second voltage; and third means for selectivelyallowing said source line to float to a level that is substantiallyequal to said first voltage.
 12. The control circuit for an SRAMaccording to claim 11, wherein said first means comprises a firstN-channel transistor.
 13. The control circuit for an SRAM according toclaim 12, wherein said second means comprises second and third N-channeltransistors, said second N-channel transistor being connected to saidsecond voltage and being connected to said source line through saidthird N-channel transistor.
 14. The control circuit for an SRAMaccording to claim 13, wherein a gate and a drain of said secondN-channel transistor are connected together.
 15. The control circuit foran SRAM according to claim 11, wherein said third voltage isapproximately a diode drop above said second voltage.
 16. A memoryleakage control method operable with a static random access memory(SRAM) that operates between a first voltage and a second voltage, saidSRAM comprising a plurality of SRAM cells arranged in rows and columns,each SRAM cell being coupled to a respective wordline, respectivecomplementary bitlines, and a source line, said method comprising:selectively connecting said source line to said second voltage;selectively connecting said source line to a third voltage that isbetween said first voltage and said second voltage; and selectivelyallowing said source line to float to a value substantially equal tosaid first voltage.
 17. The memory leakage control method according toclaim 16, wherein selectively connecting said source line to a thirdvoltage comprises connecting said source line to ground through atransistor connected to operate like a diode.
 18. The memory leakagecontrol method according to claim 16, wherein selectively connectingsaid source line to said second voltage comprises turning on anN-channel field effect transistor connected between said source line andsaid second voltage.
 19. The memory leakage control method according toclaim 16, wherein selectively allowing said source line to floatcomprises isolating said source line from said second voltage.